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Silicon Labs /EFR32MG22C224F512IM32 /SYSCFG_S /DMEM0ECCCTRL

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Interpret as DMEM0ECCCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RAMECCEN)RAMECCEN 0 (RAMECCEWEN)RAMECCEWEN

Description

Configure to set RAM ECC control.

Fields

RAMECCEN

RAM ECC Enable
RAMECCEWEN

RAM ECC Error Writeback Enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data